An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time

作者：Oh Hyunggoy^*; Han Taewoo; Choi Inhyuk; Kang Sungho

来源：IEEE Transactions on Computers, 2017, 66(1): 38-44.

DOI：10.1109/TC.2016.2561920

• Post-silicon debug
• MISR compaction
• trace buffer
• debug time

Debug time has become a major issue in post silicon debug because of the increasingly complicated nature of circuit design. However, reducing debug time is a major challenge because of the limited size of the trace buffer used to observe internal signals in the circuit. This study proposes an on-chip error detection method to overcome this challenge. The on-chip process detects the error-suspect window using the pre-calculated golden data stored in the trace buffer. This allows the selective compaction and capture of the debug data in the trace buffer during the error-containing interval. As a result, reducing the number of debug sessions significantly reduces the total debug time. The experimental results on various debug cases show significant reductions in total debug time compared to previous work.

• 出版日期2017-1-1