A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD

作者：Liu Supeng^*; Zheng Yuanjin

来源：IEEE Journal of Solid-State Circuits, 2016, 51(6): 1361-1373.

DOI：10.1109/JSSC.2016.2557810

• Digital calibration
• digital controlled oscillator
• digital phase-locked loop
• high speed counter
• injection-locked frequency divider
• time-to-digital converter

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2-23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD's multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm(2). The synthesizer covers 13.6-16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves -89 dBc/Hz and -125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps.

• 出版日期2016-6
• 单位南阳理工学院