An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

作者：Ferriss Mark^*; Plouchart Jean Olivier; Natarajan Arun; Rylyakov Alexander; Parker Ben; Tierno Jose A; Babakhani A; Yaldiz Soner; Valdes Garcia Alberto; Sadhu Bodhisatwa; Friedman Daniel J

来源：IEEE Journal of Solid-State Circuits, 2013, 48(4): 996-1008.

DOI：10.1109/JSSC.2013.2239114

• Bandwidth calibration
• frequency synthesizers
• phase locked loop
• PLL

An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of -126.5 dBc/Hz at 20.1 GHz and -124.2 dBc/Hz at 24 GHz

• 出版日期2013-4