High linearity technique for ultra-wideband low noise amplifier in 0.18 mu m CMOS technology

作者：Galal A I A^*; Pokharel R; Kanaya H; Yoshida K

来源：AEU-International Journal of Electronics and Communications, 2012, 66(1): 12-17.

DOI：10.1016/j.aeue.2011.04.010

• CMOS
• High linearity
• Low noise amplifier
• Ultra-wideband

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 mu m CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm(2), including all pads. The measured input return loss is kept below -11 dB, and the output return loss is -8 dB, from 3.1 to 10.6 GHz.

• 出版日期2012