A Quasi-Doherty SOI CMOS Power Amplifier With Folded Combining Transformer

作者：Kim Kichul^*; Lee Dong Ho; Hong Songcheol

来源：IEEE Transactions on Microwave Theory and Techniques, 2016, 64(8): 2605-2614.

DOI：10.1109/TMTT.2016.2577584

• Adaptive bias circuit (ADB)
• adaptive power cell (APC)
• adaptive power divider (APD)
• folded combining transformer (CT)
• power amplifier (PA)
• quasi-Doherty
• SOI CMOS

A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a -33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.

• 出版日期2016-8