A high efficient CTLE for 12.5 Gbps receiver of JESD204B standard

作者：Chen, Gang^*; Gong, Min; Fu, Dongbing; Zhang, Junan

来源：IEICE Electronics Express, 2018, 15(15): 20180617.

DOI：10.1587/elex.15.20180617

• SerDes
• CTLE
• high speed serial link
• electrical channel attenuation
• internal symbol interference (ISI)
• BER
• equalizer

A 12.5 Gbps continuous-time linear equalizer circuit (CTLE) constructed with two stage equalizer, three stages of limiting amplifier and designed in 55 nm CMOS technology for high speed serial interface of JESD204B standard is presented. Beside using degeneration RC pair to compensate low pass response of the channel and high frequency signal loss, the first equalizer also utilizes inductive shunt peaking technology to further extend the bandwidth of input signals. The proposed circuit was simulated with post layout parasitic extraction and achieves around 20 ps peak-to-peak jitter, 1.08 V voltage swing and a data rate of 12.5 Gbps through 10-inch FR- 4 PCB trace with the characteristic of low equalization power consumption.

• 出版日期2018-8-10
• 单位重庆理工大学