A Vertically Integrated Junctionless Nanowire Transistor

作者：Lee Byung Hyun; Hur Jae; Kang Min Ho; Bang Tewook; Ahn Dae Chul; Lee Dongil; Kim Kwang Hee; Choi Yang Kyu^*

来源：Nano Letters, 2016, 16(3): 1840-1847.

DOI：10.1021/acs.nanolett.5b04926

• Silicon nanowire (SiNW)
• gate-all-around (GAA)
• vertical integration
• junctionless transistor
• three-dimensional nonvolatile memory
• one-route all-dry etch

A vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is demonstrated on a bulk silicon wafer for the first time. The proposed VJ-FET mitigates the issues of variability and fabrication complexity that are encountered in the vertically integrated multi-NW FET (VM-FET) based on an identical structure in which the VM-FET, as recently reported, harnesses a source and drain (S/D) junction for its operation and is thus based on the inversion mode. Variability is alleviated by bulk conduction in a junctionless FET (JL-FET), where current flows through the core of the SiNW, whereas it is not mitigated by surface conduction in an inversion mode FET (IM-FET), where current flows via the surface of the SiNW. The fabrication complexity is reduced by the inherent JL structure of the JL-FET because S/D formation is not required. In contrast, it is very difficult to dope the S/D when it is positioned at each floor of a tall SiNW with greater uniformity and with less damage to the crystalline structure of the SiNW in a VM-FET. Moreover, when the proposed VJ-FET is used as nonvolatile flash memory, the endurance and retention characteristics are improved due to the above-mentioned bulk conduction.

• 出版日期2016-3