A novel ESD power supply clamp circuit with double pull-down paths

作者：Liu HongXia^*; Yang ZhaoNian; Li Li; Zhuo QingQing

来源：Science China Information Sciences, 2013, 56(10): 102401.

DOI：10.1007/s11432-012-4699-z

• ESD (electrostatic-discharge)
• clamp circuit
• duration
• false triggering
• power supply noise

Electrostatic-discharge (ESD) protection design is one of the key challenges of advanced CMOS processes. RC-triggered and MOSFET-based power supply ESD clamp circuits have been widely used to obtain the desired ESD protection ability. In this paper, a MOSFET-based ESD power clamp circuit with only 10 ns RC time constant for 0.18-mu m process is presented. A double pull-down path is proposed to avoid false triggering, reject power supply noise and reduce energy consumption. The performance of the novel clamp circuit is excellent, consuming very small layout area. The simulation results show that this clamp circuit can be used in industry.

• 出版日期2013-10
• 单位西安电子科技大学