A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes

作者：Abiri Ebrahim; Darabi Abdolreza^*

来源：Microprocessors and Microsystems, 2018, 60: 122-137.

DOI：10.1016/j.micpro.2018.04.010

• Clocked Master-Slave toggle flip-flop (M/S-TFF)
• Energy consumption-propagation delay product (EDP)
• Data activity, Corner case variations and noise immunity
• Static frequency divider (SFD)
• Microprocessor chip

In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product (PDP) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency (f(max)) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance.

• 出版日期2018-7