A Tow-Level Buffered SDRAM Controller

作者：Jin Tian^*; Li Wenxin; Hu Xiangyu

来源：3rd International Conference on Information Science and Control Engineering (ICISCE), 2016-07-08 To 2016-07-10.

DOI：10.1109/ICISCE.2016.37

• Tow-Level Buffered
• SDRAM controller
• pipelined

With the improvement of processor and SDRAM performance, the performance of SDRAM controller becomes the bottleneck of the system performance. In this paper, a Tow-Level Buffered SDRAM controller is proposed, and its design and verification are described. To some extent, the controller improves the throughput of the processor for the SDRAM memory, and provides a solution for the design of high performance system.

• 出版日期2016
• 单位兰州空间技术物理研究所; 中国空间技术研究院