A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter

作者：Kefalas N; Theodoridis G^*

来源：Integration, the VLSI Journal, 2015, 49: 65-77.

DOI：10.1016/j.vlsi.2014.10.002

• Deblocking filter
• H.264AVC
• Video compression
• Pipeline
• ASIC
• FPGA

Exploiting specific properties of the algorithm, a high-throughput pipelined architecture is introduced to implement the H.264/AVC deblocking filter. The architecture was synthesized in 0.18 mu m technology and the clock frequency and area are 400 MHz and 16.8 Kgates, respectively. Also, it is able to filter 217 and 55 Frames per second (Fps) for Full- and Ultra-HD videos, respectively. The introduced architecture outperforms similar ones in terms of frequency (1.8 x up to 4 x), throughput, (1.5 x up to 3.8 x), and Fps. Moreover, extensions to support different sample bit-depths and chroma formats are included. Also, experimental results for different FPGA families are offered.

• 出版日期2015-3