A bidirectional neural interface SoC with an integrated spike recorder, microstimulator, and low-power processor for real-time stimulus artifact rejection

作者：Limnuson Kanokwan; Lu Hui; Chiel Hillel J; Mohseni Pedram^*

来源：Analog Integrated Circuits and Signal Processing, 2015, 82(2): 457-470.

DOI：10.1007/s10470-015-0489-z

• Closed-loop neuroprostheses
• Neural recording
• Neural signal processing
• Neurostimulation
• Stimulus artifact rejection
• System-on-chip
• Template subtraction

This paper presents a neural interface system-on-chip (SoC) featuring combined spike recording, electrical microstimulation, and real-time stimulus artifact rejection (SAR) for bidirectional interfacing with the nervous system. The SoC integrates a spike-recording front-end with input noise voltage of 3.42 mu V-rms (0.5 Hz-50 kHz), microstimulating back-end for delivering charge-balanced monophasic or asymmetric biphasic current pulses of < 100 mu A with passive discharge, and mu W-level digital signal processing (DSP) unit for real-time SAR based on template subtraction. The DSP unit initializes its embedded 16b, 4 K static random-access memory with the first recorded stimulus artifact to reduce the operation time in generating an accurate artifact template signal for subtraction. Fabricated in AMS 0.35 mu m 2P/4M CMOS, the 3.1 x 3.1-mm(2) SoC has been characterized in benchtop tests and neurobiological experiments with isolated buccal ganglia of an Aplysia californica (a marine mollusk). The SoC can successfully remove mV-range stimulus artifacts with duration up to similar to 115 ms from the contaminated neural data in real time and recover A mu V-range extracellular neural spikes that occur on the tail end of the artifacts. The average root-mean-square (rms) value of the pre-processed stimulus artifact is reduced by a factor of similar to 24-30 post-processing, with DSP unit power consumption of < 25 A mu W from 1.5 V.

• 出版日期2015-2