ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies

作者：Cao Shuqing^*; Chun Jung Hoon; Beebe Stephen G; Dutton Robert W

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2010, 57(9): 2301-2311.

DOI：10.1109/TCSI.2010.2071590

• Charged device model (CDM)
• co-design methodology
• electrostatic discharge (ESD)
• field effect diode
• high-speed I/O
• integrated circuit reliability
• RF
• semiconductor diodes
• T-coil
• very fast transmission line pulses (VF-TLP).

Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed circuit protection techniques such as the T-coil based ESD design are reviewed in detail. Package-and wafer-level charged device model (CDM) correlation issues are discussed. I/O, ESD devices, and metal interconnect effects are examined using very fast transmission line pulses (VF-TLP) and TLP.

• 出版日期2010-9