A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-mu m CMOS

作者：Seo Young Hun^*; Lee Seon Kyoo; Sim Jae Yoon

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2011, 58(2): 70-74.

DOI：10.1109/TCSII.2011.2106315

• All-digital phase-locked loop (DPLL)
• phase-locked loop (PLL)
• time-to-digital converter (TDC)

A new concept of floating-point-number representation is implemented in a time-to-digital converter (TDC), which adaptively scales its resolution according to the amount of input difference. With a fixed 6-bit significand number, the TDC provides five cases of the exponent (x1, x2, x4, x8, and x16) to indicate the scale information. A digital phase-locked loop (PLL) with the TDC is implemented in a 0.18-mu m CMOS. The TDC shows the minimum resolution of 3 ps with a total conversion range of 3.5 ns, the maximum operating frequency of 80 MHz, and the power consumption of 18 mW at 75 MHz. The PLL shows a lock range of 0.9-1.25 GHz and a root-mean-square jitter of 3.5 ps at 1.2 GHz.

• 出版日期2011-2