Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations

作者：Meterelliyoz Mesut^*; Kulkarni Jaydeep P; Roy Kaushik

来源：IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(1): 2-13.

DOI：10.1109/TCAD.2009.2035535

• 6-T SRAM
• 8-T SRAM
• cache memory
• compact thermal models
• eDRAM
• performance
• robustness
• stability
• thermal analysis
• thermal aware design methodology

In scaled technologies, cache memories which are traditionally known as "cold" sections of the chip are expected to occupy a larger die area. Hence, different sections of a cache memory may experience different temperature profiles depending on their proximity to the active logic units such as the execution unit. In this paper, we performed thermal analysis of cache memories under the influence of hot-spots. In particular, 6-transistor (T) static random access memory (SRAM), 8-T SRAM, and embedded dynamic random access memory (eDRAM) cache memories were investigated. Thermal maps of the entire caches were generated using hierarchical compact thermal models while solving the leakage and temperature self-consistently. The 6-T and the 8-T SRAM bitcells were investigated in terms of stability, noise immunity, and performance under temperature variations for various technology nodes. The 3-T micro sense amplifier used in eDRAM cache memories was investigated for its robustness. Thermal-aware circuit design techniques were explored to improve cache stability under thermal gradients. Results show that, for all cache memories, spatial temperature variations have to be considered to achieve the optimal memory design.

• 出版日期2010-1