A 5.7-6.0 GHz CMOS PLL with low phase noise and-68 dBc reference spur

作者：Li, Xiaoqiang; Zhang, Jingwei; Zhang, Yuanzhi; Wang, Wenshen; Liu, Huimin^*; Lu, Chao^*

来源：AEU-International Journal of Electronics and Communications, 2018, 85: 23-31.

DOI：10.1016/j.aeue.2017.12.025

• PLL
• Reference spur
• Current mismatch
• Low phase noise

This paper presents a 5.7-6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (K-VCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7-6.0 GHz, the reference spur is -68 dBc, the phase noise levels are -109 dBc/Hz and -135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work's reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.

• 出版日期2018-2
• 单位天津理工大学