An efficient multiple precision floating-point Multiply-Add Fused unit

作者：Manolopoulos K; Reisis D^*; Chouliaras V A

来源：Microelectronics Journal, 2016, 49: 10-18.

DOI：10.1016/j.mejo.2015.10.012

• Floating-point
• Multiply-Add Fused
• Multiple precision
• VLSI

Multiply-Add Fused (MAF) units play a key role in the processor's performance for a variety of applications. The objective of this paper is to present a multi-functional, multiple precision floating-point Multiply-Add Fused (MAF) unit. The proposed MAF is reconfigurable and able to execute a quadruple precision MAF instruction, or two double precision instructions, or four single precision instructions in parallel. The MAF architecture features a dual-path organization reducing the latency of the floating-point add (FADD) instruction and utilizes the minimum number of operating components to keep the area low. The proposed MAF design was implemented on a 65 nm silicon process achieving a maximum operating frequency of 293.5 MHz at 381 mW power.

• 出版日期2016-3