摘要

A fault-tolerant adjustable speed drive (ASD) topology is introduced in this paper. A conventional ASD topology is modified to address: 1) drive vulnerability to semiconductor device faults; 2) input voltage sags; 3) motor vulnerability to effects of long leads; and 4) minimization of common-mode (CM) voltage applied to the motor terminals. These objectives are attained by inclusion of an auxiliary IGBT inverter leg, three auxiliary diodes, and isolation-reconfiguration circuit. The design and operation of the proposed topology modifications are described for different modes: 1) fault mode, 2) active CM suppression mode, and 3) auxiliary sag compensation (ASC) mode. In case of fault and sag, the isolation and hardware reconfiguration are performed in a controlled manner using triacs/antiparallel thyristors. In normal operation, the auxiliary leg is controlled to actively suppress CM voltage. For inverter IGBT failures (short circuit and open circuit), the auxiliary leg is used as a redundant leg. During voltage sags, the auxiliary leg, along with auxiliary diodes, is operated as a boost converter. A current-shaping control strategy is proposed for the ASC mode. A detailed analysis of CM performance of the proposed topology is provided, and a new figure of merit, CM distortion ratio (CMDR), is introduced to compare the attenuation of CM voltage with that of a conventional ASD topology. The output filter design procedure is outlined. A design example is presented for an 80 kW ASD system, and simulation results validate the proposed auxiliary leg based fault-tolerant scheme. Experimental results from a scaled prototype rated at 1 hp are discussed in this paper.

  • 出版日期2015-5