An analysis for fault-tolerant 3D processor Arrays using 1.5-track switches

作者：Horita Tadayoshi^*; Katou Yuuji; Takanami Itsuo

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2008, E91A(2): 623-632.

DOI：10.1093/ietfec/e91-a.2.623

• 3D mesh-connected processor arrays
• 1.5-track switches
• reconfiguration
• fault tolerance
• redundancy

This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of M, and M,, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where M(t) and M(s) are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.

• 出版日期2008-2
• 单位香港理工大学