Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs

作者：Yue Xicai^*

来源：Microelectronics Journal, 2013, 44(6): 473-478.

DOI：10.1016/j.mejo.2013.03.011

• Successive approximation register (SAR)
• ADC
• Binary-weighted DAC capacitor array
• Common centroid layout
• Process matching
• Thermal noise

The layout area of an SAR ADC is mainly occupied by its DAC capacitor array. Since there are 2(N) matched unit capacitors employed for a binary-weighted N-bit DAC, selecting a small unit capacitance is the key to reducing the layout area of the capacitor array, and accordingly reduce the total area of an SAR ADC for size-constrained implantable or wearable applications. In this paper the matching error and thermal noise of the capacitor array are considered systematically for the whole SAR ADC to determine the minimum unit capacitance. The statistical analysis shows that the matching error of the capacitor array depends not only on the matching parameter of the given process but also on the confidence level of the design, while thermal noise analysis shows that thermal noise of the capacitor array does not equal that of either the unit capacitor or the total capacitance of the capacitor array. The calculations for the matching error and thermal noise of a 10-bit DAC show that although the matching error is 7 times bigger, thermal noise which consumes 1/8 error budget should not be ignored for determining the reliable minimum unit capacitance. An iterative algorithm is proposed to find the minimum value when both matching error and thermal noise are considered. A 10-bit SAR ADC adopting an 89.44 fF poly-poly unit capacitor in the 0.35 mu m CMOS process validated the method.

• 出版日期2013-6