A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier

作者：Akter Md Shakil^*; Makinwa Kofi A A; Bult Klaas

来源：IEEE Journal of Solid-State Circuits, 2018, 53(4): 1115-1126.

DOI：10.1109/JSSC.2017.2778277

• Amplifier
• analog linearization technique
• analog-to-digital converter (ADC)
• capacitive degeneration
• cross-coupled capacitors
• digital nonlinearity calibration
• dynamic residue amplifier
• integrator
• split-capacitor technique

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV(pp, diff) and 4x gain, it achieves -100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 mu W at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26x compared with that of state-of-the-art high-linearity amplifiers.

• 出版日期2018-4