Rank-Level Parallelism in DRAM

作者：Shin Wongyu^*; Jang Jaemin; Choi Jungwhan; Suh Jinwoong; Kwon Yongkee; Moon Youngsuk; Kim Lee Sup

来源：IEEE Transactions on Computers, 2017, 66(7): 1274-1280.

DOI：10.1109/TC.2017.2654339

• DRAM
• main memory
• MiB
• middle buffer
• mRLP
• rank-level parallelism

DRAM systems are hierarchically organized: Channel-Rank-Bank. A channel is connected to multiple ranks, and each rank has multiple banks. This hierarchical structure facilitates creating parallelisms in DRAM. The current DRAM architecture supports bank-level parallelism; as many rows as banks can be moved simultaneously at bank-level. However, rank-level parallelism is not supported. For this reason, only one column can be accessed at a time, although each rank has its own data bus that can carry a column. Namely, current DRAM operations do not exploit the structural opportunity created by multiple ranks. We, therefore, propose a novel DRAM architecture supporting rank-level parallelism. Thereby, as many columns as ranks can be moved concurrently at rank-level. In this paper, we illustrate the rank-level parallelism and its benefit in DRAM operations.

• 出版日期2017-7-1