An Adaptive-Rate Error Correction Scheme for NAND Flash Memory

作者：Chen Te Hsuan^*; Hsiao Yu Ying; Hsing Yu Tsao; Wu Cheng Wen

来源：27th IEEE VLSI Test Symposium, 2009-05-03 To 2009-05-07.

DOI：10.1109/VTS.2009.24

• Error correction
• flash memory
• BCH code
• memory fault tolerance
• memory management

ECC has been widely used to enhance Hash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level.

• 出版日期2009
• 单位清华大学