ASIC Implementation of one level 2D DWT and 2D DWT in Hybrid Wave-Pipelining & Pipelining

作者：Adhinarayanan V^*; Gopalakrishnan S; Shabeer H A

来源：Journal of Scientific & Industrial Research, 2015, 74(11): 609-613.

• FPGA
• SOC
• ASIC
• DWT
• Lifting
• Constant co-efficient multiplier

Pipeline system requires clock routine complexity and clock skews between different parts of the system. Higher operating frequencies may be obtained in digital system using wave pipelining which permits clock frequencies. This requires proper selection of clock periods and clock skews for latched output of combinational logic circuit at the stable periods. Hybrid scheme is aimed at combination of advantage of pipelining and wave pipelining. Hence, we propose the design and implementation of hybrid wave 2D DWT pipelining using lifting scheme and system computational of one level 2D DWT implemented using the following techniques pipelining, non pipelining and wave pipelining. From the result, it is concluded that Hybrid pipelining is faster than non pipeline and requires less area and less clock, routing complexity and lower power compare to pipeline and also it is observed that wave pipeline circuit is faster than non pipeline circuit.

• 出版日期2015-11