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摘要
This paper discusses the design and implementation of a pseudo-differential high-speed and highly linear novel Source-Follower Buffer in 0.35 mu m CMOS. The high linearity of Source Follower is achieved by means of a cascode transistor and an auxiliary structure to mitigate impact of channel modulation and parasitic capacitances. The new architecture consumes 10 mW from a 3.3-V supply and it achieves a total harmonic distortion of -74.5 dB at 100MHz, yielding 12-b resolution. Design methodology, simulation and experimental results are presented.
- 出版日期2013-3
