A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

作者：Perktold L^*; Christiansen J

来源：Journal of Instrumentation, 2014, 9(01): C01060.

DOI：10.1088/1748-0221/9/01/C01060

• VLSI circuits
• Analogue electronic circuits
• Front-end electronics for detector readout

The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than +/- 0.9 LSB and integral-non-linearity (INL) of better than +/- 1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology.

• 出版日期2014-1