An FPGA-Based Linear All-Digital Phase-Locked Loop

作者：Kumm Martin^*; Klingbeil Harald; Zipf Peter

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57(9): 2487-2497.

DOI：10.1109/TCSI.2010.2046237

• All-digital phase-locked loop (ADPLL)
• direct digital synthesizer (DDS)
• field-programmable gate array (FPGA)
• PLL

In this paper, an all-digital phase-locked loop (ADPLL) is presented, and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator is given.

• 出版日期2010-9