Analog to digital converter for high density neural signal recording front-end in 90 nm

作者：Zarifi Mohammad Hossein^*; Farshchi Shahin; Frounchi Javad

来源：Analog Integrated Circuits and Signal Processing, 2011, 68(3): 349-355.

DOI：10.1007/s10470-011-9612-y

• Time-based ADC
• Floating-point ADC
• Pipeline ADC
• High speed latch comparator
• Offset cancellation
• Variable gain amplifier
• Implantable systems

High-fidelity recording of neural signals requires varying levels of signal gain to capture low-amplitude single-unit activity in the presence of high-amplitude population activity. A floating-point approach has been used to widen the dynamic range of analog-to-digital converters (ADC) designed for this application. In this paper we present an ADC, designed for multi-channel, portable neural signal recording systems. To achieve low power consumption, small die area and wide dynamic range, an ADC based on a time-based algorithm, combined with a floating-point pipelined structure has been designed and simulated. A conventional variable-gain amplifier (VGA) stage has been eliminated in favor of a reference-current in a time-based ADC architecture. The 12-b pipelined time-based floating-point ADC has been designed with a 7-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The mantissa is determined by a uniform 7-b pipelined time-based analog to digital converter. The ADC chip was designed and simulated in a 90 nm CMOS process, which occupies an active area of 360 mu m x 550 mu m, and consumes 7.8 mu W at 1.2 V in full-scale conversion.

• 出版日期2011-9