Novel Sidewall Interconnection Using a Perpendicular Circuit Die for 3-D Chip Stacking

作者：Kim Sun Rak^*; Lee Jae Hak; Lee Seung S

来源：IEEE Transactions on Components, Packaging and Manufacturing Technology, 2015, 5(9): 1265-1272.

DOI：10.1109/TCPMT.2015.2457419

• Edge tracing technique
• sidewall interconnection
• stacked chip
• stud bump
• wafer level

A new sidewall interconnection approach using a perpendicular circuit die is implemented in this paper; this device can be applied to the fabrication of chip stacks. Thermal stress analysis is implemented using the ABAQUS software package to investigate the reliability issues of a stacked chip. The analysis indicates that it has little effect on the reliability of the stacked chip. Experiments were conducted by stacking four chips each having a thickness of 180 mu m; the configuration of the pads on the test chip is similar to that of a memory chip. The stacked chips were fabricated successfully by dicing the wafer. Vertical interconnection was made by thermo-compression bonding a perpendicular circuit die on an edge of the chip stack. The interconnection quality of the stacked chip was examined through 3-D images obtained via Computed Tomography (CT) and X-ray imagery. The images show that the interconnections were made successfully. The electrical contact resistance of the interconnection is comparable with that obtained using the wire bonding.

• 出版日期2015-9