A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting

作者：Kramer Martin^*; Janssen Erwin; Doris Kostas; Murmann Boris

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2017, 64(2): 116-120.

DOI：10.1109/TCSII.2016.2554858

• Analog-to-digital converter (ADC)
• complementary metal-oxide semiconductor (CMOS)
• redundancy
• successive approximation register (SAR)

We present a successive approximation register analog-to-digital converter (ADC) that employs a comparator with time-varying noise performance, realized by changing the integration time of a G(m) - C preamplifier. This approach allows us to relax precision and enhance speed during non-critical decisions, leading to an aggregate speed-up of 22% compared to a conventional design. The ADC operates at 30 MS/s, achieves a peak signal-to-noise and distortion ratio of 77.2 dB, and consumes 38 mW from 1.2 V/2.5 V supplies, corresponding to a Schreier FOM of 163.1 dB (161.6 dB at Nyquist). The proof-of-concept converter is implemented in a 40-nm LP complementary metal-oxide semiconductor process and occupies 0.24 mm(2).

• 出版日期2017-2