A 247 mu W 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface

作者：Lim Soo Bin^*; Lee Hyun Woo; Song Junyoung; Kim Chulwoo

来源：IEEE Journal of Solid-State Circuits, 2013, 48(3): 711-723.

DOI：10.1109/JSSC.2013.2242251

• Calibration
• data confliction
• deep power down
• delay-locked loop (DLL)
• dynamic random access memory (DRAM)
• GDDR6
• half period detector
• leakage power
• power down
• PVT variation
• self-aligner
• self-refresh
• short current
• synchronous mirror delay (SMD)
• through silicon via (TSV)

Among the stacked dies using through silicon via (TSV), data conflictions occur due to process mismatches, which decrease the data valid window and consume unwanted power due to the short circuit current. This paper presents the DLL-based data self-aligner (DBDA), which reduces data conflictions among stacked dies. The stacked dies employing the proposed DBDAs automatically align their data output timings without relying on any control signals from the master die or an extra signal among the stacked die. The DBDA reduces the data confliction time (tDC) due to process, voltage and temperature (PVT) variations from 500 ps to 50 ps and thereby reduces the short current from 3.62 mA to 0.41 mA. The proposed DBDA has two operation modes: the synchronous self-align mode (SSAM), in which the data is aligned in the external clock domain and the asynchronous self-align mode (ASAM). The lock time of DBDA is less than 20 cycles in SSAM. Additionally, the lock detector (LD) and proposed re-calibrator help the DBDA to find the optimal calibration period under temperature variation. They also reduce the calibration current of DBDA by 45.5%. A prototype DBDA implemented in 130 nm CMOS technology dissipates 247 mu W for 800 Mb/s/pin. For reduction of the leakage current during the power down mode or the self-refresh mode, this paper proposes a leakage current controller, which reduces the leakage power by 90.5%.

• 出版日期2013-3