A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS

作者：Liang Jinghang^*; Zhou Zhiyin; Han Jie; Elliott Duncan G

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2013, 60(1): 108-115.

DOI：10.1109/TCSI.2012.2215696

• Alias-Locked Loop (ALL)
• Phase-Locked Loop (PLL)
• ring oscillator
• subsample

A 6.0-13.5 GHz alias-locked loop (ALL) frequency synthesizer is designed and simulated in 130 nm CMOS. Using an aliasing divider, the ALL architecture makes it possible to create high-speed frequency synthesis circuits without relying on a traditional divider clocked at f(VCO) in the feedback path. In this implementation, a new architecture of high frequency ring oscillator is proposed with a feedforward path and selectable modes of operation for different frequency ranges. This ring oscillator provides both a high oscillating frequency and a wide tuning range. Simulation results have shown that the design synthesizes the desired frequencies and consumes 30.01 mW @ 13.0 GHz with a 1.2 V power supply.

• 出版日期2013-1