A test set embedding approach based on twisted-ring counter with few seeds

作者：Zhou Bin^*; Ye Yi zheng; Li Zhao lin; Zhang Jian wei; Wu Xin chun; Ke Rui

来源：Integration, the VLSI Journal, 2010, 43(1): 81-100.

DOI：10.1016/j.vlsi.2009.06.001

• Twisted-ring counter
• Built-in self-test
• Test data storage
• Test application time
• Test power dissipation

Test data storage, test application time and test power dissipation increase dramatically for single stuck-at faults while tens of million gates are integrated in a System-on-a-Chip (SoC), which makes implementing fault testing for embedded cores based SoC become a challenging task. To further reduce test data storage, test application time and test power dissipation, this paper presents a new test set embedding approach based on twisted-ring counter (TRC) with few seeds. This approach includes two improvements. The first is that an efficient seed-selection algorithm is employed to exploit the high-density unspecified bits in the deterministic test set and so the test data storage for complete coverage of single stuck-at faults is minimized. The second is that a novel test-sequence-reduction scheme based on shifting seeds is proposed to reduce test application time that in turn reduces test power dissipation. Compared with the conventional approach, experiments on ISCAS'89 benchmark circuits show that the proposed approach requires 65% less test data storage, 68% shorter test application time and 67% less test power dissipation. Moreover, its hardware overhead is very small.

• 出版日期2010-1
• 单位哈尔滨工业大学; 深圳清华大学研究院