Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

作者：Abdulrazzaq Bilal I^*; Ibrahim Omar J; Kawahito Shoji; Sidek Roslina M; Shafie Suhaidi; Yunus Nurul Amziah Md; Lee Lini; Halin Izhal Abdul

来源：Sensors (Switzerland), 2016, 16(10): 1593.

DOI：10.3390/s16101593

• delay step
• delay range
• time jitter
• Delay-Locked Loop (DLL)
• charge pump
• Capacitor-Reset Circuit (CRC)

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 mu m Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture's circuit is 0.1 mW when the DLL is operated at 2 GHz.

• 出版日期2016-10