A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery

作者：Yin Wenjing^*; Inti Rajesh; Elshazly Amr; Talegaonkar Mrunmay; Young Brian; Hanumolu Pavan Kumar

来源：IEEE Journal of Solid-State Circuits, 2011, 46(12): 3163-3173.

DOI：10.1109/JSSC.2011.2168873

• Digital clock and data recovery circuit
• hybrid analog/digital phase detection
• jitter transfer bandwidth
• linear loop dynamics

A digital clock and data recovery circuit (CDR) employs hybrid analog/digital phase detection to achieve linear loop dynamics and to eliminate the nonlinearity and quantization error of a bang-bang phase detector. The proposed architecture achieves constant jitter transfer bandwidth independent of input data jitter and reduces the sensitivity to digitally-controlled oscillator's frequency quantization error and consecutive identical digits. The hybrid phase detection scheme also helps decouple jitter generation from jitter transfer characteristics of the CDR. The prototype digital CDR fabricated in 0.13 mu m CMOS technology achieves error-free operation (BER < 10(-12)) for PRBS data sequences ranging from 2(7)-1 to 2(31)-1 sequence lengths over 0.5 Gb/s to 3.2 Gb/s data rates. At 2.5 Gb/s, the CDR consumes 7 mW power from a single 1.2 V supply and the recovered clock jitter is 5.7 ps rms.

• 出版日期2011-12