摘要
In this paper, a delay fault model for multilayer graphene nanoribbon (GNR)-based power interconnects for 16-nm International Technology Roadmap for Semiconductors technology node is developed for both top-contact GNR and side-contact GNR. The delay fault model is developed for different temperature considering the impact of scattering parameters. It is shown that side-contact GNR-based power interconnects can reduce the delay fault significantly in comparison with that of Cu and top-contact GNR interconnects at local, intermediate, and global lengths for a wide range of chip operating temperatures from 233K to 378K.
- 出版日期2018-6