Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

作者：Yan, Aibin^*; Huang, Zhengfeng; Yi, Maoxiang; Xu, Xiumin; Ouyang, Yiming; Liang, Huaguo

来源：IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 25(6): 1978-1982.

DOI：10.1109/TVLSI.2017.2655079

• Circuit reliability
• double-node upset (DNU)
• radiation hardening
• single-node upset (SNU)
• soft error

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.

• 出版日期2017-6
• 单位合肥工业大学; 安徽大学