A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

作者：Prasad K Hari; Sukhwani Menka; Saxena Pooja; Chandratre V B^*; Pithawa C K

来源：Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment , 2014, 737: 117-121.

DOI：10.1016/j.nima.2013.11.018

• Time-to-digital conversion (TDC)
• Vernier method
• Aplication specific integrated circuit (ASIC)
• PVT
• Calibration
• SPI

A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 mu m commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based On the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 mu s and precision (sigma) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

• 出版日期2014-2-11