A Fast ULV Logic Synthesis Flow in Many-V-t CMOS Processes for Minimum Energy Under Timing Constraints

作者：Bol David^*; Hocquet Cedric; Regazzoni Francesco

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2012, 59(12): 947-951.

DOI：10.1109/TCSII.2012.2231034

• Design automation
• digital integrated circuits
• timing closure
• ultra-low power
• ultra-low voltage

Ultra-low-voltage (ULV) logic offers the opportunity to operate at the minimum-energy point (MEP) for applications with low-to-medium speed requirements. Unfortunately, the critical design constraint of achieving a reliable timing closure at the target frequency of the application becomes very complex in the wide design space of ULV including supply (V-dd) and threshold (V-t) voltage selection as well as netlist optimizations from the synthesis. In this paper, we propose a fast synthesis flow to accurately predict the V-dd/V-t MEP under strict timing constraints. Compared to an exhaustive search for the MEP under timing constraints based on numerous library recharacterizations and synthesis steps for all V-dd/V-t pairs, the proposed ULV flow dramatically speeds up the design process. Indeed, it requires a single library recharacterization and only three synthesis steps. Results obtained for several ITC%26apos;99 benchmarks under a wide range of timing constraints from 0.1 to 30 MHz in 65-nm LP/GP CMOS demonstrate that the proposed flow has a less than 10% energy penalty with respect to the absolute MEP computed with an exhaustive search and energy savings enhanced up to 2.4x compared to a conventional flow with V-dd scaling only.

• 出版日期2012-12