摘要
This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-mu m CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz.
- 出版日期2010-10