Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology

作者：Akbar Ehsan Pour Ali; Haghparast Majid^*; Navi Keivan

来源：Microelectronics Journal, 2011, 42(8): 973-981.

DOI：10.1016/j.mejo.2011.05.007

• Reversible logic
• ZS series gates
• Reversible array multiplier
• Wallace sign multiplier

Today, reversible logic is emerging as an intensely studied research topic, having applications in diverse fields, such as low-power design, optical information processing, and quantum computation. In this paper, we have proposed two reversible Wallace signed multiplier circuits through modified Baugh-Wooley approach, which are much better than the two available counterparts in all the terms. The multiplier is an essential building block for the construction of computational units of quantum computers. Besides, we need signed multiplier circuits for numerous operations. However, only two reversible signed multiplier circuits have been presented so far. In the first proposed architecture, our goals are to decrease the depth of the circuit and to increase the speed of the circuit. In the second proposed circuit, we aimed to improve the quantum cost, garbage outputs, and other parameters. All the proposed circuits are in the nanometric scales and can be used in the design of very complex systems.

• 出版日期2011-8