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摘要
A low-noise and high-gain down-conversion mixer fabricated via a 0.13 mu m CMOS process is presented. The proposed mixer is based on the folded-type topology and includes an inverter transconductance, a switched biasing circuit and an LO switch, which improve the conversion gain and noise figure. Moreover, the switched biasing circuit is combined with a current bleeding circuit to reduce power consumption and flicker noise. A conversion gain of 24.75 dB and a noise figure of 4.59 dB were achieved at 2.1 GHz of RF while consuming 1.93 mW from a supply voltage of 1.0 V.
- 出版日期2012-11-8
