Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking

作者：Lee Chang Chun; Lin Yu Min; Hsieh Chia Ping; Liou Yan Yu; Zhan Chau Jie; Chang Tao Chih; Wang Chien Ping

来源：Microelectronic Engineering, 2016, 156: 24-29.

DOI：10.1016/j.mee.2016.01.040

• 3D-ICs
• Ultra-thin chip
• Microbump
• FEA
• Packaging

This study presents a process for wafer handling and robust assembly, which is a novel pre-molding technology applied to assembled stacked modules prior to chip thinning. These steps aim to overcome severe challenges of achieving extra-thin thickness as low as 10 mu m for chip stacking in 3D-IC module, such as mechanical damage that appears during chip grinding. A packaging vehicle is fabricated to demonstrate the feasibility of the proposed approach. Analysis results show that underfill flexibility can relieve expansion of the produced stress to establish a 3D simulation model. The top layer of the outermost microjoint has the most serious reliability concern under a load of temperature change. Moreover, failure estimation and mechanical reliability are also performed via 3D nonlinear finite element analysis.

• 出版日期2016-4-20