An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology

作者：Matsuno Tetsuro^*; Fujimoto Daisuke; Kosaka Daisuke; Hamanishi Naoyuki; Tanabe Ken; Shiochi Masazumi; Nagata Makoto

来源：IEICE - Transactions on Electronics, 2010, E93C(6): 820-826.

DOI：10.1587/transele.E93.C.820

• noise emulation
• substrate noise
• power supply noise
• signal integrity
• substrate coupling
• power integrity

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm(2) in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

• 出版日期2010-6