A CMOS K-Band 6-bit Attenuator With Low Phase Imbalance for Phased Array Application

作者：Zhang, Lin; Zhao, Chenxi^*; Zhang, Xiaoning; Wu, Yunqiu; Kang, Kai

来源：IEEE Access, 2017, 5: 19657-19661.

DOI：10.1109/ACCESS.2017.2750203

• Attenuator
• CMOS
• phase imbalance

A 6-bit digital-controlled attenuator with low phase imbalance for a K-band phased array system is presented in this paper. To decrease the insertion phase difference, the proposed design adopts a phase correction capacitor in the shunt branch of the conventional switched T/Pi structure. The capacitor and the parallel resistor compose a phase compensation network to correct the insertion phase error. The attenuator is designed and fabricated in 0.18 mu m CMOS process. From 19 to 21 GHz, the insertion loss is 7.2-8 dB. The rms phase imbalance is less than 3.8 degrees over 19-21 GHz. The attenuator has a maximum attenuation range of 32 dB with 0.5-dB step (64 states). The core cell chip size is 1.32 mm X 0.34 mm excluding pads.

• 出版日期2017
• 单位电子科技大学