A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications

作者：Santoro Francesco^*; Kuhn Ruediger; Gibson Neil; Rasera Nicola; Tost Thomas; Graeb Helmut; Wicht Bernhard; Brederlow Ralf

来源：IEEE Journal of Solid-State Circuits, 2018, 53(6): 1856-1868.

DOI：10.1109/JSSC.2018.2799964

• Buck
• dc-dc
• fast wake-up
• low energy
• low power
• minimized capacitor
• wake-up energy

This paper presents a dc-dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc-dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130-nm CMOS technology with an area of only 0.14 mm(2). It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.

• 出版日期2018-6