Embedded Vernier TDC with sub-nano second resolution using fractional-N PLL

作者：Bengtsson Lars^*

来源：Measurement, 2017, 108: 48-54.

DOI：10.1016/j.measurement.2017.05.038

• Time-to-digital converter
• Phase-locked loop
• Vernier
• FPGA
• Fractional-N PLL

A novel implementation technique for Vernier-based time-to-digital converters is reported. It is based on fractional-N phase-locked loops which allows the design of Vernier clocks with very close frequencies. The Vernier registers comparing counter values have been implemented in hardware in order to guarantee minimum detection latency of the moment of coincidence. Two Vernier clocks with close frequencies increment two 24-bit counters in a Cyclone V FPGA. A Vernier TDC with a demonstrated time resolution of 476 ps is reported. It is also established that the time resolution limit that can be achieved with the suggested design is 10 ps.

• 出版日期2017-10