A nearly constant delay and low power VLSI design of a pipeline Reed-Solomon encoder for storage and communication systems

作者：Wen, Chia Sheng^*; Chen, Yan Haw; Trieu Kien Truong; Hsiao, Shen Fu

来源：Journal of the Chinese Institute of Engineers, 2013, 36(6): 771-786.

DOI：10.1080/02533839.2012.742751

• error-correcting coding
• Reed-Solomon code
• Lagrange interpolation formula
• linear feedback shift register
• pipeline

Linear feedback shift register (LFSR) is a common method used in the design of Reed-Solomon (RS) encoders. Most previous LFSR-based articles have focused on the design of finite field multipliers and the throughput improvement of the RS encoders. However, these articles have some problems. First, the fan-out of the feedback register grows with respect to the increase of the error-correction capability, leading to longer encoding time. Second, in applications that require high-throughput, parallel implementations are usually adopted, which result in huge chip area. This article presents a new pipelined encoder architecture for systematic RS code, which has a nearly constant delay with less than 10% increase in cycle time for higher error-correction capability. The key technique behind this encoding technique is based on the modified polynomial of the Lagrange interpolation formula. It not only reduces the number of finite field multipliers, but also increases performance. Moreover, we propose a method of low computation complexity for the implementation of the constant multipliers in order to save area and power. Compared to the conventional LFSR architectures over the (204, 188, t = 8) RS code, the proposed encoder design reduces the critical path delay by 71% and the power consumption by 44%. Because of the high-throughput and low latency, the new design is readily adaptable for use in many applications such as RAID 6, CD, VCD, DVD, and high definition television, especially for storage and communication applications.

• 出版日期2013
• 单位中山大学