A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors

作者：Zhou Zhijun^*; Warr Paul

来源：Analog Integrated Circuits and Signal Processing, 2017, 93(2): 237-243.

DOI：10.1007/s10470-017-0982-7

• CMOS
• Integrated resistor
• Segmented layout guarding
• Parasitic capacitance

Within integrated circuit design, parasitic capacitance associated with the realisation of a resistor can limit circuit performance for certain applications, such as the analogue-to-digital converter. In this paper, a segmentation guarding layout technique is introduced that offers the circumvention of the parasitic capacitance of integrated resistors. The segmentation guarding technique is demonstrated on both diffusion and polysilicon integrated resistors.

• 出版日期2017-11