A 5.6 ppm/degrees C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point

作者：Jiang Jize^*; Shu Wei; Chang Joseph S

来源：IEEE Journal of Solid-State Circuits, 2017, 52(3): 623-633.

DOI：10.1109/JSSC.2016.2627544

• Curvature compensation
• high-precision
• MOSFET-only
• sub-1-V
• system-on-chip
• voltage reference
• wide-band high power supply rejection ratio (PSRR)
• zero-temperature coefficient (ZTC) point

This paper describes an MOSFET-only voltage reference realized in 65-nm CMOS featuring a temperature coefficient (TC) of 5.6 ppm/degrees C from -40 degrees C to 125 degrees C, a power supply rejection ratio of 87 dB from dc up to 800 kHz (and 75 dB at 1 MHz), a minimum supply voltage of 0.8 V, and a power dissipation of 13 mu W. These attributes are achieved by exploiting the zero-TC point of an MOSFET and combining it with a novel curvature-compensation technique, an active attenuator, and an impedance-adapting frequency compensation scheme.

• 出版日期2017-3
• 单位南阳理工学院